1. Field of the Art
The present invention generally relates to the field of integrated circuit design, and more specifically, to the placement and routing of the elements of an integrated circuit design.
2. Description of the Related Art
In integrated circuit fabrication, lithographic techniques are often employed to create circuit features. In order to satisfy demand for smaller circuits consuming less power, fabrication techniques are continually pushed in the direction of producing smaller and smaller features. Existing lithographic technology is capable of creating circuit features of size of similar magnitude to that of the wavelength of light used to create the features themselves. As circuit features become smaller, common optical effects such as diffusion, diffraction, and dispersion begin to significantly influence the results achieved by the fabrication. When not properly accounted for, these optical effects can cause differences between the circuit layout and the circuit as fabricated. These differences can potentially affect the functionality of the circuit, such as the leakage current and timing performance. In certain circumstances, these optical effects can result in catastrophic yield loss.
To account for these optical effects, fabrication processes employ optical proximity correction. Optical proximity correction predistorts the image that will be lithographically imprinted so that the fabricated circuit may be closer in realization to the circuit as designed.
However, optical proximity correction must make assumptions about the fabrications conditions. In practice, the conditions used to fabricate a circuit will rarely match these optimal conditions exactly. Variation in the lithographic process (“lithographic variation”), such as variation in the exposure and in the focus of the lithographic process, tends to reduce the effectiveness of optical proximity correction. Even with optical proximity correction, certain fabrication conditions can potentially affect the functionality of the fabricated circuit.
Certain circuit patterns are more sensitive to the effects of lithographic variation than other circuit patterns. The placement and routing of a circuit will affect the functionality, timing performance, and leakage current of the circuit under lithographic variation. Lithographic fabrication can be improved by designing the physical layout between circuit elements to include more robust and less lithographically sensitive circuit patterns.
Physical synthesis tools sometimes use restrictive design rules to limit the placement of circuit elements to patterns and relationships that are known to have a high probability of successful lithographic fabrication. However, restrictive design rules significantly limit the place and route tool, and applying generalized rules often results in sub-optimal designs, as the rules are followed even in circumstances when they are not strictly necessary. While restrictive design rules improve the probability of successful lithographic fabrication, they are often overly restrictive and result in a significant increase in the area occupied by a circuit. As reducing circuit size is a goal of most integrated circuit design, the increase in circuit size caused by restrictive design rules is usually an undesirable result.
From the above, there is a need for a system and method to evaluate the optical effects that will occur during lithography and to place and route circuit elements in a manner that will result in successful lithographic fabrication.